Existing machines are known to operate in superscalar mode in which two or more instructions are fetched from a program memory in the same machine cycle and then executed by different execution units. Commonly such instructions are located in adjacent memory positions and fetched from memory by a single fetch operation. Machines are also known to operate in very long instruction word (VLIW) mode. Such words may include a larger number of instructions retrieved from memory as a single word at a single word address. Instructions which may be included together in a single VLIW instruction are carefully controlled by software techniques to ensure that they avoid compatibility problems or data dependency problems between the instructions forming the word.
In computer systems a plurality of instructions may be executed in parallel and in pipelined operations. Data dependency may arise between two or more instructions which are executed in parallel or in a pipelined operation.
It is an object of the present invention to provide an improved computer system for detecting and resolving data dependence between instructions for parallel execution. Embodiments of the invention may provide a very high rate of instruction execution while avoiding a complex programming model for the software tool chain and assembly programmer.
In real-time operation the instruction scheduling should be deterministic, i.e., that the hardware does not do too much “intelligent” rescheduling of instructions which are uncontrollable (and non-deterministic) because this makes the programmer/software toolchain's task extremely difficult when the real-time nature of the application has to be respected.